Design Name | Top_module |
Device, Speed (SpeedFile Version) | XCR3064XL, -6 (6.0) |
Date Created | Tue May 06 14:03:13 2008 |
Created By | Timing Report Generator: version I.34 |
Copyright | Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
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Min. Clock Period | 5.200 ns. |
Max. Clock Frequency (fSYSTEM) | 192.308 MHz. |
Limited by Cycle Time for catode1_MC.Q | |
Clock to Setup (tCYC) | 5.200 ns. |
Setup to Clock at the Pad (tSU) | -0.400 ns. |
Clock Pad to Output Pad Delay (tCO) | 15.100 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
TS1002 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 5.2 | 104 | 104 |
AUTO_TS_P2P | 0.0 | 15.1 | 18 | 18 |
AUTO_TS_P2F | 0.0 | 4.8 | 5 | 5 |
AUTO_TS_F2P | 0.0 | 9.1 | 131 | 131 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
carry<0>.Q to carry<0>.D | 0.000 | 5.200 | -5.200 |
carry<0>.Q to carry<1>.D | 0.000 | 5.200 | -5.200 |
carry<0>.Q to carry<2>.D | 0.000 | 5.200 | -5.200 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
clkin to segment<0> | 0.000 | 15.100 | -15.100 |
clkin to segment<1> | 0.000 | 15.100 | -15.100 |
clkin to segment<2> | 0.000 | 15.100 | -15.100 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
btn to s_a0/stop_out.D | 0.000 | 4.800 | -4.800 |
btn to start_s.D | 0.000 | 4.800 | -4.800 |
btn to s_a0/current_state_FFd3.D | 0.000 | 4.300 | -4.300 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
catode1.Q to segment<0> | 0.000 | 9.100 | -9.100 |
catode1.Q to segment<1> | 0.000 | 9.100 | -9.100 |
catode1.Q to segment<2> | 0.000 | 9.100 | -9.100 |
Clock | fEXT (MHz) | Reason |
---|---|---|
btnsel | 200.000 | Limited by Clock Pulse Width for btnsel |
catode1_MC.Q | 192.308 | Limited by Cycle Time for catode1_MC.Q |
clkin | 192.308 | Limited by Cycle Time for clkin |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
btn | -0.400 | 1.200 |
Destination Pad | Clock (edge) to Pad |
---|---|
segment<0> | 12.900 |
segment<1> | 12.900 |
segment<2> | 12.900 |
segment<3> | 10.200 |
segment<4> | 10.200 |
segment<5> | 10.200 |
segment<6> | 10.200 |
Destination Pad | Clock (edge) to Pad |
---|---|
segment<0> | 15.100 |
segment<1> | 15.100 |
segment<2> | 15.100 |
segment<3> | 12.400 |
segment<4> | 12.400 |
segment<5> | 12.400 |
segment<6> | 12.400 |
reset_s | 11.900 |
start_s | 9.200 |
catode1 | 4.000 |
catode2 | 4.000 |
Source | Destination | Delay |
---|---|---|
carry<0>.Q | carry<0>.D | 5.200 |
carry<0>.Q | carry<1>.D | 5.200 |
carry<0>.Q | carry<2>.D | 5.200 |
carry<0>.Q | q<11>.D | 5.200 |
carry<0>.Q | q<13>.D | 5.200 |
carry<0>.Q | q<14>.D | 5.200 |
carry<0>.Q | q<5>.D | 5.200 |
carry<0>.Q | q<7>.D | 5.200 |
carry<0>.Q | q<9>.D | 5.200 |
carry<1>.Q | carry<1>.D | 5.200 |
carry<1>.Q | carry<2>.D | 5.200 |
carry<1>.Q | q<11>.D | 5.200 |
carry<1>.Q | q<13>.D | 5.200 |
carry<1>.Q | q<14>.D | 5.200 |
carry<1>.Q | q<9>.D | 5.200 |
carry<2>.Q | carry<2>.D | 5.200 |
carry<2>.Q | q<13>.D | 5.200 |
carry<2>.Q | q<14>.D | 5.200 |
q<0>.Q | carry<0>.D | 5.200 |
q<0>.Q | q<1>.D | 5.200 |
q<0>.Q | q<3>.D | 5.200 |
q<10>.Q | carry<2>.D | 5.200 |
q<10>.Q | q<11>.D | 5.200 |
q<10>.Q | q<9>.D | 5.200 |
q<11>.Q | carry<2>.D | 5.200 |
q<11>.Q | q<11>.D | 5.200 |
q<11>.Q | q<9>.D | 5.200 |
q<12>.Q | q<13>.D | 5.200 |
q<12>.Q | q<14>.D | 5.200 |
q<13>.Q | q<13>.D | 5.200 |
q<13>.Q | q<14>.D | 5.200 |
q<14>.Q | q<13>.D | 5.200 |
q<14>.Q | q<14>.D | 5.200 |
q<15>.Q | q<13>.D | 5.200 |
q<15>.Q | q<14>.D | 5.200 |
q<1>.Q | carry<0>.D | 5.200 |
q<1>.Q | q<1>.D | 5.200 |
q<1>.Q | q<3>.D | 5.200 |
q<2>.Q | carry<0>.D | 5.200 |
q<2>.Q | q<1>.D | 5.200 |
q<2>.Q | q<3>.D | 5.200 |
q<3>.Q | carry<0>.D | 5.200 |
q<3>.Q | q<1>.D | 5.200 |
q<3>.Q | q<3>.D | 5.200 |
q<4>.Q | carry<1>.D | 5.200 |
q<4>.Q | q<5>.D | 5.200 |
q<4>.Q | q<7>.D | 5.200 |
q<5>.Q | carry<1>.D | 5.200 |
q<5>.Q | q<5>.D | 5.200 |
q<5>.Q | q<7>.D | 5.200 |
q<6>.Q | carry<1>.D | 5.200 |
q<6>.Q | q<5>.D | 5.200 |
q<6>.Q | q<7>.D | 5.200 |
q<7>.Q | carry<1>.D | 5.200 |
q<7>.Q | q<5>.D | 5.200 |
q<7>.Q | q<7>.D | 5.200 |
q<8>.Q | carry<2>.D | 5.200 |
q<8>.Q | q<11>.D | 5.200 |
q<8>.Q | q<9>.D | 5.200 |
q<9>.Q | carry<2>.D | 5.200 |
q<9>.Q | q<11>.D | 5.200 |
q<9>.Q | q<9>.D | 5.200 |
s_a0/current_state_FFd3.Q | s_a0/stop_out.D | 5.200 |
s_a0/current_state_FFd3.Q | start_s.D | 5.200 |
s_a0/stop_out.Q | s_a0/stop_out.D | 5.200 |
s_a0/stop_out.Q | start_s.D | 5.200 |
start_s.Q | carry<0>.D | 5.200 |
start_s.Q | q<1>.D | 5.200 |
start_s.Q | q<3>.D | 5.200 |
start_s.Q | s_a0/stop_out.D | 5.200 |
start_s.Q | start_s.D | 5.200 |
carry<0>.Q | q<10>.D | 4.700 |
carry<0>.Q | q<12>.D | 4.700 |
carry<0>.Q | q<15>.D | 4.700 |
carry<0>.Q | q<4>.D | 4.700 |
carry<0>.Q | q<6>.D | 4.700 |
carry<0>.Q | q<8>.D | 4.700 |
carry<1>.Q | q<10>.D | 4.700 |
carry<1>.Q | q<12>.D | 4.700 |
carry<1>.Q | q<15>.D | 4.700 |
carry<1>.Q | q<8>.D | 4.700 |
carry<2>.Q | q<12>.D | 4.700 |
carry<2>.Q | q<15>.D | 4.700 |
q<0>.Q | q<2>.D | 4.700 |
q<12>.Q | q<15>.D | 4.700 |
q<13>.Q | q<15>.D | 4.700 |
q<14>.Q | q<15>.D | 4.700 |
q<1>.Q | q<2>.D | 4.700 |
q<4>.Q | q<6>.D | 4.700 |
q<5>.Q | q<6>.D | 4.700 |
q<8>.Q | q<10>.D | 4.700 |
q<9>.Q | q<10>.D | 4.700 |
start_s.Q | q<0>.D | 4.700 |
start_s.Q | q<2>.D | 4.700 |
Source | Destination | Delay |
---|---|---|
qdiv<0>.Q | catode2.D | 5.200 |
qdiv<1>.Q | catode2.D | 5.200 |
qdiv<2>.Q | catode2.D | 5.200 |
catode1.Q | catode2.D | 4.700 |
qdiv<0>.Q | catode1.D | 4.700 |
qdiv<0>.Q | qdiv<1>.D | 4.700 |
qdiv<0>.Q | qdiv<2>.D | 4.700 |
qdiv<1>.Q | catode1.D | 4.700 |
qdiv<1>.Q | qdiv<2>.D | 4.700 |
qdiv<2>.Q | catode1.D | 4.700 |
Source Pad | Destination Pad | Delay |
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